The present invention relates to semiconductor devices and methods of manufacturing semiconductor devices. The present invention has particular applicability to double-gate devices.
The escalating demands for high density and performance associated with ultra large scale integration semiconductor devices require design features, such as gate lengths, below 100 canometers (nm), high reliability and increased manufacturing throughput. The reduction of design features below 100 nm challenges the limitations of conventional methodology.
For example, when the gate length of conventional planar metal oxide semiconductor field effect transistors (MOSFETs) is scaled below 100 nm, problems associated with short channel effects, such as excessive leakage between the source and drain, become increasingly difficult to overcome. In addition, mobility degradation and a number of process issues also make it difficult to scale conventional MOSFETs to include increasingly smaller device features. New device structures are therefore being explored to improve FET performance and allow further device scaling.
Double-gate MOSFETs represent new structures that have been considered as candidates for succeeding existing planar MOSFETs. In double-gate MOSFETs, two gates may be used to control short channel effects. A FinFET is a recent double-gate structure that exhibits good short channel behavior. A FinFET includes a channel formed in a vertical fin. The FinFET structure may be fabricated using layout and process techniques similar to those used for conventional planar MOSFETs.
Implementations consistent with the present invention provide methodology for forming a gate in a FinFET device. The gate may be formed without damaging other regions of the FinFET device, such as source/drain regions.
Additional advantages and other features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The advantages and features of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of forming a gate in a FinFET device. The method includes forming a resist mask over a portion of a silicon on insulator (SOI) wafer, where the SOI wafer includes a silicon layer on an insulating layer. The method also includes etching the silicon layer not covered by the resist mask to form a fin, where the fin has a plurality of side surfaces and a top surface, forming a gate oxide on the side surfaces and the top surface of the fin and depositing a gate layer over the fin. The method further includes depositing a dielectric layer over the gate layer, depositing a bottom anti-reflective coating (BARC) layer over the dielectric layer and forming a gate mask over the BARC layer. The method also includes etching the BARC layer, where the etching terminates on the dielectric layer and etching the gate layer to form the gate.
According to another aspect of the invention, a method of manufacturing a semiconductor device is provided. The method includes forming a fin structure on an insulating layer, the fin structure having a plurality of side surfaces, a top surface and a bottom surface, forming source and drain regions and forming a gate dielectric on at least a first and second side surface of the fin. The method also includes depositing a gate material over the insulating layer and the fin structure, forming a dielectric layer over the gate material and depositing an anti-reflective coating (ARC) layer over the dielectric layer. The method further includes forming a gate mask over the ARC layer, etching the ARC layer, where the etching terminates on the dielectric layer and etching the gate material to form at least one gate.
Other advantages and features of the present invention will become readily apparent to those skilled in this art from the following detailed description. The embodiments shown and described provide illustration of the best mode contemplated for carrying out the invention. The invention is capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings are to be regarded as illustrative in nature, and not as restrictive.